1. Field of the Invention
This invention relates to a complex dielectric film and a semiconductor device especially suitable for use in high-integrated, high-density semiconductor integrated circuit devices.
2. Description of the Prior Art
A basic two-layered wiring structure used in a conventional semiconductor integrated circuit device is explained with reference to a schematic diagram of FIG. 1.
As shown in FIG. 1, in the conventional semiconductor integrated circuit device, a first inter-layer insulation film 102 is formed on a silicon substrate 101. The first inter-layer insulation film 102 has a contact hole 102a at a predetermined portion, and a first plug 103 is embedded in the contact hole 102a. The first plug 103 is connected to a diffusion layer (not shown) formed in a selective portion of the silicon substrate 101 aligned with the contact hole 102a. A first wiring layer 104 overlies the first plug 103 and the first inter-layer insulation film 102. The first wiring layer 104 is connected to the first plug 103, and covered by a second inter-layer insulation film 105. The second inter-layer insulation film 105 has a contact hole 105a at a predetermined portion, and a second plug 106 is embedded in the contact hole 105a. A second wiring layer 107a is formed on the second plug 106, and another second wiring layer 107b is formed in a close relation with the second wiring layer 107a on the second inter-layer insulation film 105. A third inter-layer insulation film 108 overlies the second wiring layers 107a and 107b.
A barrier metal 109 underlies the first wiring layer 104, second wiring layers 107a, 107b, first plug 103 and second plug 106, and an anti-reflection film 110 overlies the first wiring layer 104 and the second wiring layers 107a, 107b.
The semiconductor integrated circuit device shown in FIG. 1 is manufactured in a process explained below. First formed on the entire surface of the silicon substrate 101 is the first inter-layer insulation film 102 by chemical vapor deposition(CVD) or physical vapor deposition(PVD). After that, the contact hole 102a is made by patterning the first inter-layer insulation film 102 by lithography and etching. Next, the first plug 103 is embedded in the contact hole 102a. Then, a conductive film for making the wiring layer is formed on the entire surface in the same manner as used before, and the first wiring layer 104 is formed by patterning the conductive film by using the same techniques. After that, the second inter-layer insulation film 105 is formed on the entire surface by the same method, and then patterned to make the contact hole 105a using the same technique. Then, the second plug 106 is embedded in the contact hole 105a. After that, another conductive film for making the wiring layer is formed on the entire surface by the same method, and then patterned to make the wiring layers 107a, 107b by the same technique. After that, the third inter-layer insulation film 108 is formed on the entire surface in the same manner. Explanation is omitted on formation of the barrier metal 109 and the anti-reflection film 110.
In this manner, by repeating the process of depositing an inter-layer insulation film, patterning the insulation film, depositing a conductive film for making a wiring layer, and patterning the conductive film, a two-layered wiring structure is made.
An essential feature of the wiring structure used in the conventional semiconductor integrated circuit device shown in FIG. 1 lies in that, paying a particular attention to the second wiring layers 107a, 107b in a face-to-face arrangement, the third inter-layer insulation film 108, typically made of a silicon oxide (SiO.sub.2) material, is formed to fill the gap between the second wiring layers 107a, 107b.
Although the semiconductor integrated circuit device shown in FIG. 1 has a two-layered wiring structure, current technologies are developing semiconductor integrated circuit devices having a five to six-layered wiring structures for higher-integrated and higher-density devices.
Along with a progress in higher-integration and higher-density of semiconductor integrated circuit devices, elements and areas or regions of the devices become more and more micro-sized and close-located. Resulting problems are explained below, taking a semiconductor integrated circuit device having a three-layered wiring structure shown in FIG. 2 where identical or equivalent parts or elements as those of the semiconductor integrated circuit device shown in FIG. 1 are labelled with common reference numerals. Numerals 1071, 107b, 107c denote second wiring layers, 111 a third wiring layer, and 112 a fourth inter-layer insulation film.
As shown in FIG. 2, as high integration and high density of semiconductor integrated circuit devices progress, distances among the second wiring layers 107a, 107b, 107c decreases. Due to this, inter-wiring capacitances C.sub.1, C.sub.1 ' increase, and this causes a delay of transmission of electric signals among the second wiring layers 107a, 107b, 107c due to their capacitance-resistance coupling. Moreover, an increase in inter-wiring capacitances C.sub.2, C.sub.3 occurs also among the first wiring layer 104, second wiring layers 107a, 107b, 107c, and third wiring layer 111 due to their decreased distances, cross-talk or other interference of electric signals occurs among these wiring layers.
These undesirable phenomena can be partly overcome by using improvements disclosed in Japanese Patent Laid-Open Nos. 57-190331 and 63-179548 which propose an open hole (or an open hollow) to the wiring layers, or by using an aerial wiring disclosed in Japanese Patent Laid-Open Nos. 56-19636 and 57-43444. In the conventional wiring structure shown in FIG. 2, such problems can be partly overcome also by using special materials for making the first inter-layer insulation film 102, second inter-layer insulation film 105 and third inter-layer insulation film 108, which have smaller dielectric constants than that of SiO.sub.2 conventionally used as the material of inter-layer insulation films, namely, silicon boron nitride (SiBN), oxy-fluoride silicon (SiOF) and polyimide fluoride which are disclosed in Japanese Patent Laid-Open Nos. 62-156822, 2-77127 and 4-328126 as materials for improving conventional techniques. However, for higher-integrated and higher-density semiconductor integrated circuit devices, the problems cannot be removed sufficiently by the existing approaches, either using the improved architecture or using special materials.